The present invention relates to information read/write devices such as magnetic disk drives or optical disk drives, and more particularly, to information read/write devices intended mainly to reduce electric power consumption.
The development of high-density recording technologies associated with magnetic disk drives, optical disk drives, and the like, has made rapid progress in recent years. In response to this, information read/write devices having capacities from at least several gigabytes to several tens of gigabytes, despite the fact that the diameters of the media used are as small as about 25 to 45 mm, have been put into practical use. These small-size large-capacity information read/write devices are now commonly used in portable computers, portable musical disc players, portable video viewers/recorders, and other application apparatus that assumes hand-held use. These types of application apparatus have their power supplies depending mainly on batteries. The capacities of existing batteries, however, are far from being up to a level at which they satisfy the nonstop operation time that the user or the application program requires. For information read/write devices and their application apparatus, therefore, enhancing the performance-power consumption ratios of these products' internal mechanisms and internal circuits is in urgent need for reduced power consumption.
A typical configuration example of an application apparatus (first conventional technology) which uses a conventional magnetic disk drive is shown in FIG. 1. The application apparatus in this configuration example is broadly divided into two blocks. One of the two blocks is a drive 199 (magnetic disk drive) that receives issued commands through a storage interface 101 and operates in accordance with the received commands, and the other is a host 198 that issues commands to the drive 199. In general, the circuits of the host 198 and those of the drive 199 are mounted as independent circuit modules, which are coupled via the element, such as connector or cable, that forms part of the physical entity of the storage interface 101. Parallel ATA interface standards (these standards are disclosed in Non-Patent Document 1 (ANSI INCITS 361-2002 AT Attachment—6 with Packet Interface), for example), serial ATA interface standards (these standards are disclosed in Non-Patent Document 2 (Serial ATA: High-Speed Serialized AT Attachment Revision 1.0), for example), Small Computer System Interface (SCSI) standards (these standards are disclosed in Non-Patent Document 3 (ANSI INCITS 362-2002 Information Technology—SCSI Parallel Interface-4 (SPI-4)), for example), or the like are widely known, and proliferated, as the standards adopted for the storage interface 101. Based on these standards, the commands issued from the host 198 to the drive 199, the status data returned from the drive 199 to the host 198, the write data transferred from the internal RAM-1 115 of the host 198 to write the data onto a recording medium, and the data read out from the recording medium to store the data into the internal RAM-1 115 of the host 198, are transferred over the storage interface 101. On the storage interface 101, the rectangular-wave digital signals of relatively large amplitude that have frequencies from several tens of megahertz to several gigahertz are transmitted since rapid data transfer is requested through signal paths relatively long in transmission distance. To the internal processor-1 111 of the host 198, a drive compliant with the parallel ATA interface standards proliferating at a particularly rapid pace is mounted as one type of register file, and commands and status data are transferred in basic units of eight bits to the drive in parallel. The data read/written is also handled as access to a specific register, and 512 bytes of block data is sequentially transferred as an indivisible basic transfer unit in an 8-bit or 16-bit pattern. That is to say, the host 198 cannot make random access in units of less than 512 bytes of data to the internal RAM-2 124 of the drive 199 in any form or by any means.
The host 198 is constructed with the processor-1 111 as its central element, and the processor-1 111 mainly executes the application programs (not shown) that determine the external functions of the application apparatus. The processor-1 111 uses a memory control circuit 114 to access the RAM-1 115 or other internal resources of the host 198. Data transfer arbitration circuit 113 arbitrates data transfer between a DMA control circuit 112, an external interface circuit 110, a storage interface circuit 116, the memory control circuit 114, and a ROM-1 117. The data transfer arbitration circuit 113 also adjusts bands and latency between the above elements. The host 198 is connected to the drive 199 only via the storage interface circuit 116, and as mentioned above, the host 198 conducts control of the drive 199, based on commands and protocol specifications, through the storage interface 101. The drive 199 that undertakes a storage function in the application apparatus has a processor-2 122 different from the processor-1 111 of the host 198. The processor-2 122 mainly executes the read/write channel control programs (not shown) that have been loaded into the RAM-2 124 or a ROM-2 124, and mechanism control programs (not shown). The processor-2 122 also controls a head/disk assembly 126 through a head/disk control circuit 125. In this case, the sharable RAM-1 115 and RAM-2 124 are mounted in or on semiconductor memory elements such as dynamic RAMs (DRAMs) or static RAMs (SRAMs).
When the application apparatus is started by power-on or restarted by a resetting operation or the like, the processor-1 111 accesses the ROM-1 117 via the memory control circuit 114 and the data transfer arbitration circuit 113 and then starts executing an initializing program (not shown) that is prestored within the ROM-1 117. When the initialization of each resource within the host 198 is completed by the execution of the initializing program, the processor-1 111 attempts loading an application program from the drive 199 into the RAM-1 115 via the memory control circuit 114, the data transfer arbitration circuit 113, and the storage interface circuit 116. Instead, in an application apparatus of a larger scale, its initializing program may load an operating system program (not shown) from a drive 199 before an application program is loaded, and then the operating system program may load and execute the application program. When the host 198 starts an initializing operation, the drive 199 is also notified of this via the storage interface 101 and the drive 199 also starts an initializing operation. First, the processor-2 122 executes an initializing program (not shown) that is prestored within the ROM-2 124 and initializes each internal resource of the drive 199. Additionally, when necessary, the processor-2 122 operates the head/disk control circuit 125 and the memory control circuit 123 in accordance with the initializing program, then loads an additional program from a recording medium (not shown) into the RAM-2 124, and executes the program. When the initializing process and the loading of the additional program are completed, the drive 199 enters a stand-by state to wait for a command to be issued from the host 198.
When the initialization of both the host 198 and the drive 199 is completed, the processor-1 111 finally executes the application program that was loaded into the RAM-1 115, and issues a read command via the storage interface 101 in order to further read in only necessary data of the application program from the drive 199. In this case, instead of the read command, a write command may be issued through the storage interface 101 in order to process, and write into the drive 199, data that has been acquired from an external interface 100 through the external interface circuit 110 beforehand. The operation of each section during the issuance of the read command or of the write command is described below.
First, when a command is issued from the host 198 via the storage interface 101, a command analysis/status display circuit 121 receives the command through a host interface circuit 120. If the results of command analyses by the command analysis/status display circuit 121 and the processor-2 122 indicate that the command is a write command, the processor-2 122 instructs the memory control circuit 123 to transfer the data to be sent from the host interface 120 to the RAM-2 124. Thus, write data (not shown) is temporarily stored from the host 198 into the RAM-2 124. At this time, the DMA control circuit 112 inside the host 198 operates in accordance with an instruction from the processor-1 111 and then the write data is transferred from the RAM-1 115 via the storage interface circuit 116. Concurrently with this, the processor-2 122 instructs the head/disk control circuit 125 to conduct the positioning of a read/write head (not shown) with respect to the recording medium, setup of writing conditions, and other operations. The processor-2 122 subsequently instructs the memory control circuit 123 to transfer the write data from the RAM-2 124 to the head/disk control circuit 125, and finally, the write data is written onto (recorded on) the recording medium.
If the command analysis results indicate that the command is a read command, the processor-2 122 instructs the head/disk control circuit 125 to conduct the positioning of the read/write head with respect to the recording medium, setup of reading conditions, and other operations. The processor-2 122 also instructs the memory control circuit 123 to transfer data from the head/disk control circuit 125 to the RAM-2 124, and write data (not shown) is temporarily stored into the RAM-2 124. After storage of the write data, the processor-2 122 further instructs the memory control circuit 123 to transfer the data to be sent from the RAM-2 124 to the host interface circuit 120, and read data is sent to the host 198 via the storage interface 101. At this time, the DMA control circuit 112 inside the host 198 operates in accordance with an instruction from the processor-1 111, and finally, the read data is stored into the RAM-1 115 via the storage interface circuit 116.
Also, according to Patent Document 1 (Japanese Patent Laid-Open No. 2004-146036), the processor-1 111 within the host 198 constantly monitors the status of the application apparatus exterior via the external interface circuit 110 and the external interface 100. On detecting the occurrence of an event which requires emergency processing during the operation of the application apparatus, the processor-1 111 conducts a normal command-issuing process to issue a necessary command to the drive 119 via the memory control circuit 114, the data transfer arbitration circuit 113, and the storage interface circuit 116. That is, for example, if battery power consumption progresses and the time for which the application apparatus can operate runs short, the host 198 makes the drive 199 reliably save the important data required for application apparatus operation (e.g., metadata associated with file storage in the drive 199, operational state data on the application apparatus, data settings, and the like) on the recording medium. The host 198 also issues a stopping command to the drive 199 to retract the read/write head (moves the read/write head to a safe location free from the danger of the head being brought into contact with the recording medium by, for example, vacuum attraction, or colliding with the medium). If the physical overturn of an application system is detected, the read/write head is also retracted in the above manner.
As heretofore described, in the application apparatus employing the information read/write device based on the first conventional technology, only command issuance from the host 198, based on the specifications of the storage interface 101 has been used as a trigger for the drive 199 to conduct read/write or other operations, irrespective of the configuration of the host 198. That is, it has been necessary for the trigger to be given from the host 198 before a constituent element of the drive 199 became able to actively access an internal resources of the host 198 via the storage interface 101 (e.g., before the processor-2 122 became able to make random access to the RAM-1 115 within the host 198) or before a constituent element of the drive 199 became able to directly control the operation of the processor-1 111 within the host 198 (e.g., before the processor-2 122 became able to stop the execution of an activity/job by the processor-1 111). In addition, when the host 198 was to conduct data read/write operations on the drive 199, it has been absolutely necessary for the data transfer to be repeated twice, once between the RAM-1 115 and the RAM-2 124 and once between the RAM-2 124 and the head/disk assembly 126, with the RAM-2 in between.